1. Field of the Invention
The present invention relates to an invalid signal filtering method and a shifter utilizing the method, and particularly relates to an invalid signal filtering method and a shifter utilizing the method that can discard an invalid signal.
2. Description of the Prior Art
For DDR3, a mechanism is developed to filter out an illegal or invalid read command signal, which can be a read command signal given to an inactive bank. The decoded legal or valid read command signals generate “ValidRead” that is gated with dll-domain, which indicates a clock is processed by a DLL line thus is different from the clock inside the device, read that is sent to Qed shifter for sampling. The above decoding is a relatively slow process and may not occur before the dll-domain read exits the Delay-Line especially for shallow lock point situations. In this case, the rising edge of the “legal” read gets chopped off, leading to setup violation at Qed where the read fails to get sampled.
For an electronic device with higher operation frequency such as DDR4, the above-mentioned issue becomes more serious, since the decoding speed can not follow up the increasing operation speed. Therefore, a new approach to filter valid read command signal is needed.